1. Field of the Invention
The invention relates to a combined CMOS and NPN output pull-up circuit, and more particularly to such a circuit for use with Transiently-Saturated Full-Swing BiCMOS (TS-FS-BiCMOS) circuits.
2. Discussion of the Related Art
A TS-FS-BiCMOS circuit is an output stage that enables high-speed full-swing operation at a supply voltage of less than approximately 2 V. Such a circuit is reported in: IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL.27, NO.11, NOVEMBER 1992, p. 1568 Hiraki et Al.
In this circuit, one wants to achieve fast output switching times with full-swing operation. In order to achieve fast output switching, output bipolar transistors must be used and in order to realize full-swing operation, output MOS transistors must be used. This circuit achieves fast output switching with full-swing operation by connecting the respective output bipolar and output MOS transistors in parallel.
To achieve an output logic state transition, the appropriate bipolar transistor is saturated i.e. fully conducting, until its respective MOS transistor is fully conducting, at which point, the bipolar transistor is turned off and it is the respective MOS transistor that provides the steady state output voltage; hence the term `Transiently-Saturated Full-Swing`.
FIG. 1 illustrates a detailed circuit diagram of a TS-FS-BiCMOS circuit as taught by the aforementioned article. It includes two CMOS command stages 10 and 12. Command stage 10 provides a transient control signal to the base terminal 14 of an output pull-up PNP bipolar transistor TP1. Command stage 12 provides a transient control signal to the base terminal 16 of an output pull-down NPN bipolar transistor TN1. The emitter terminals of the bipolar transistors TP1 and TN1 are connected to a positive supply rail V+ and a negative supply rail V-, respectively, whilst their collector terminals are both connected to an output terminal Vout.
Command stage 10 comprises two parallel connected P-MOS transistors MP1 and MP2 and two series-connected N-MOS transistors MN1 and MN2. The sources of transistors MP1 and MP2 are connected to the positive voltage supply rail V+ whilst their drains 14 are connected to the base of the bipolar transistor TP1 and the drain of transistor MN1. The source 20 of transistor MN1 is connected to the drain of transistor MN2 whose source is connected to the negative voltage supply rail V-. The gates of transistors MP1 and MN1 are connected to an input terminal Vin. The gates of transistors MP2 and MN2 both receive a feedback signal Vfb. Transistors MP1 and MN1 are connected in such a manner that they form an inverter 21, the output of which controls transistor TP1.
Command stage 12 includes two series connected P-MOS transistors MP3 and MP4 and two parallel connected N-MOS transistors MN3 and MN4. The sources of transistors MN3 and MN4 are connected to the negative supply rail V- whilst their drains 16 are connected to the base of the bipolar transistor TN1 and the drain of transistor MP4. The source 22 of transistor MP4 is connected to the drain of transistor MP3 whose source is connected to the positive supply rail V+. The gates of transistors MP4 and MN4 are also connected to the input terminal Vin. The gates of transistors MP3 and MN3 also receive the feedback signal Vfb. Transistors MP4 and MN4 are connected in such a manner that they form an inverter 23, the output of which controls transistor TN1.
An output latch 18 includes two CMOS inverters 24 and 26.
Inverter 24 comprises an N-MOS transistor MN6 and a P-MOS transistor MP6 connected between the supply rails V- and V+. The gate terminals of transistors MN6 and MP6 are connected together to form the input of inverter 24, whilst their respective drain terminals are connected together to form its output.
Inverter 26 comprises an N-MOS transistor MN5 and a P-MOS transistor MP5 connected between the supply rails V- and V+. The gate terminals of transistors MN5 and MP5 are connected together to form the input of inverter 26, whilst their respective drain terminals are connected together to form its output.
The output Vout is connected to the input of inverter 24 and the output of inverter 26. The output of inverter 24 is connected to the input of inverter 26 and provides the feedback signal Vfb.
The operation of the circuit of FIG. 1 will now be described.
Due to the symmetry of the two command stages, only the pull-up operation of command stage 10 will be described in detail, since the pull-down operation (command stage 12) is easily deduced thereupon by one skilled in the art.
Firstly, assume that the voltage at the input Vin is held at a steady low state i.e. approximately V-. The output Vout is then also at a steady low state. Thus, it can clearly be seen that the output Vfb of inverter 24 is held at a steady high state i.e. approximately V+.
With reference to command stage 10, transistors MP1 and MN2 are on i.e. conducting, and transistors MP2 and MN1 are off i.e. non-conducting. Transistor MP1 provides a low impedance path between its source and drain i.e. between the positive supply rail V+ and the base 14 of transistor TP1. Therefore, transistor TP1 is off and provides a high impedance path between its emitter and collector i.e. between the positive supply rail V+ and the output Vout. Transistor MN2 provides a low impedance path between the negative supply rail V- and the source 20 of transistor MN1. Transistor MN1 provides a high impedance path between the positive and negative supply rails, respectively V+ and V-. The output Vout is held low by transistor MN5 of inverter 26, whose input is held high by transistor MP6 of inverter 24.
Consider a voltage signal with a rising edge arriving at the input Vin, such that the low state of the input Vin changes to a high state i.e. approximately V+. In such a situation transistor MP1 turns-off and transistor MN1 turns-on, whilst the conduction states of transistors MP2 and MN2 remain the same during, and for some short period after, the state transitions of transistors MP1 and MN1. Also, transistors MP4 and MN4, within command stage 12, turn off and turn on, respectively.
Now that transistor MP1 has been turned off, there exists a high impedance path between the positive supply rail V+ and the base 14 of transistor TP1.
Since transistors MN1 and MN2 are both conducting, a low impedance path exists between the base 14 of transistor TP1 and the negative supply rail V-. As a consequence, transistor TP1 turns on. Thus, transistor TP1 supplies current to the output Vout and charges the input capacitance of inverter 24. The voltage at the output Vout will increase even though transistor MN5 is still conducting, since in practice, transistor TP1 is designed to source more current than transistor MN5 is designed to sink.
As the voltage at the output Vout rises, the output Vfb of inverter 24 goes low, which turns off transistors MN5 of inverter 26 and MN3 of command stage 12 and turns on transistors MP5 of inverter 26 and MP3 of command stage 12. Therefore, transistor MP5 provides a steady state low impedance path and low voltage drop between the positive supply rail V+ and the output Vout. The low state of the output Vfb of inverter 24 also turns off the N-MOS transistor MN2 of command stage 10 and turns on its P-MOS transistor MP2. Therefore, the PNP transistor TP1 is turned off, since its base 14 is at a voltage of approximately V+.
With a circuit of the type illustrated in FIG. 1, the rise time of the output signal Vout is primarily dependant upon the switching speed of the output PNP transistor TP1: the switching speed of transistor TP1 is affected by such device parameters as the current gain-bandwidth product (Ft), parasitic capacitances, and parasitic resistances, which in turn are dependent upon the type of process used to fabricate the PNP transistor TP1.
Hiraki et al pointed out, in the above cited article, the practical drawback of using a low switching speed PNP transistor and recommends that a high performance PNP transistor be used to pull-up the output signal.
Hiraki et al state that in order to fabricate a practical (i.e. commercially viable) TS-FS-BiCMOS circuit, a pull-up PNP transistor with a high frequency performance, comparable to that of a pull-down NPN transistor, will be essential. This, Hiraki et al go on to state, entails using vertically processed NPN and PNP transistors for the output bipolar stage. However, it appears from the article that a vertically processed pull-up PNP transistor will complicate the fabrication process. The complexity of the fabrication process for introducing a vertically processed pull-up PNP transistor arises from the fact that the collector of this PNP transistor would need to be isolated from the substrate, and in order to achieve this, an isolated well would need to be created.